In the field of silicon CMOS (complementary metal-oxide semiconductor) fabrication, the use of metal gate is being considered. It is preferable that different metals are used for PMOS and NMOS devices so that the work functions can be optimized for each type of device. Changes in work function will affect the threshold voltage (VT). For PMOS devices, it is desirable for the work function to be close to the silicon valence band edge of 5.2 eV, whereas for NMOS devices it is desirable for the work function to be close to the silicon conduction band edge of 4.1 eV. Furthermore, the materials should be thermally stable at the temperatures used to activate the subsequently formed source and drain regions.
If the materials chosen do not have the desired work function, short channel effects, including increased DIBL (drain induced barrier lowering) may undesirably occur. For example, there may be exacerbated VT roll-off and increased subthreshold swing.
However, current materials being considered for the gates for the PMOS devices and NMOS devices do not satisfy the above requirements. Therefore, a need exists for a structure that has the desired work functions for the PMOS or NMOS device and a process of forming such structure.
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